1. Technical Field
The present invention relates to a semiconductor device having a through-electrode and a method of manufacturing the same.
2. Related Art
In recent years, for the purpose of high integration of semiconductor elements, three-dimensional mounting of laminating semiconductor elements onto one another is carried out. In order to meet such a technique, a through-electrode is provided in the substrate of a semiconductor device. As a method of forming a through-electrode, there are techniques disclosed in Japanese Laid-open Patent Publications Nos. 63-127550, 2005-294582, and 2008-53568, for example.
The technique disclosed in Japanese Laid-open Patent Publication No. 63-127550 is such that a through-hole is formed in a GaAs substrate having an oxide film and the source electrode formed on a front surface so as to reach the source electrode, an Au film is formed in the through-hole by electron gun vapor deposition, and a through-electrode is formed by non-electrolytic plating. Here, in this technique, a back surface electrode is separately formed after the through-electrode is formed.
The technique disclosed in Japanese Laid-open Patent Publication No. 2005-294582 is such that a through-electrode with a conductive small-diameter plug and a conductive large-diameter plug is formed. The small-diameter plug is located on the front surface side of the substrate, and the large-diameter plug is located on the back surface side of the substrate. The end part of the small-diameter plug is incorporated in the large-diameter plug. Here, in this technique, the bump to be the back surface electrode is integrally formed with the large-diameter plug.
The technique disclosed in Japanese Laid-open Patent Publication No. 2008-53568 is such that a seeding layer is formed on the lower part of the side surface of the through-hole and on the bottom surface of the through-hole, and a through-electrode is formed by forming a plating layer using this seeding layer. The through-electrode and the conductive pattern formed on the insulating layer located on the front surface of the substrate are connected with each other by an electrode plug buried in the insulating layer. Here, in this technique, the bump to be the back surface electrode may be integrally formed with the through-electrode.
However, according to the technique disclosed in Japanese Laid-open Patent Publication No. 63-127550, the through-electrode and the back surface electrode are separately formed. In the technique disclosed in Japanese Laid-open Patent Publication No. 63-127550, one can conceive of integrally forming the bump and the through-electrode by continuing the non-electrolytic plating for forming the through-electrode as it is. However, by non-electrolytic plating, the plating layer grows isotropically. For this reason, when this method is adopted, the distance from the central axis of the bump to the circumference is larger by the amount of the height of the bump than that of the through-electrode, so it is needed to enlarge the pitch of the through-electrode for preventing short-circuit of the bumps. Therefore, this method cannot be adopted.
Also, according to the technique disclosed in Japanese Laid-open Patent Publication No. 2005-294582, a small-diameter plug is used as a part of the through-electrode, so it is difficult to reduce the resistance of the through-electrode. Also, according to the technique disclosed in Japanese Laid-open Patent Publication No. 2008-53568, the conductive pattern and the through-electrode are connected with each other by an electrode plug, so the resistance between them has been high.
In this manner, according to the techniques disclosed in Japanese Laid-open Patent Publications Nos. 63-127550, 2005-294582, and 2008-53568, it cannot be possible to reduce simultaneously the resistance between the conductive pattern on the insulating layer and the through-electrode, and to form integrally the through-electrode and the bump which is the back surface electrode.